A Lateral Double-diffusion Metal Oxide Semiconductor field effect transistor is abbreviated as a LDMOS.
A Complementary Metal Oxide Semiconductor is abbreviated as a CMOS.
A Bipolar Transistor is abbreviated as a Bipolar.
The Bipolar, the CMOS and the LDMOS all belong to semiconductor devices, and these three semiconductor devices can be fabricated in the same chip in a process, where an integrated circuit product in which the three semiconductor devices are integrated in a single chip is referred to as a BCD (Bipolar-CMOS-DMOS) chip. The LDMOS device is the most complicated in structure among these three devices integrated in the BCD chip.
The highest operating voltage of the BCD chip is equal to the highest operating voltage of the LDMOS integrated therein. As per the operating voltage of a BCD, the BCD with an operating voltage above 200 volts is typically referred to as a high-voltage BCD, in other words, one or more LDMOS devices at an operating voltage above 200 volts have to be integrated in the high-voltage BCD.
The device performance of a high-voltage LDMOS directly decides the performance of the entire high-voltage BCD chip, and the device structure and manufacturing method of the high-voltage LDMOS directly decides the process complexity of the entire high-voltage BCD chip.
An LDMOS is consisted of a body area, a source area, a drain area, a buffer layer, a gate oxide layer and a poly-silicon gate, where the source area, the drain area and the poly-silicon gate correspond respectively to three electrodes which are a source, a drain and a gate, and the buffer layer is configured to improve voltage robustness of the drain, and the highest rated operating voltage of the LDMOS becomes higher with a higher breakthrough voltage of the drain (the highest voltage withstood by the drain).
However the inventors of this application have identified during making of a technical solution in embodiments of the invention at least the following technical problems in the prior art:
In the prior art, as illustrated in FIG. 4 and FIG. 5, a N-type epitaxial layer is typically used as a longitudinal voltage-withstanding buffer layer in the high-voltage LDMOS integrated device, and the N-type epitaxial layer area located right below the N+ drain area tends to be depleted and broken through upon a reverse bias, so the breakthrough voltage of the drain and consequently the operating voltage of the high-voltage LDMOS integrated device has to be improved by increasing the thickness of the N-type epitaxial layer, but the use of the epitaxial layer and an increase in thickness of the epitaxial layer for an improvement in operating voltage of the high-voltage LDMOS integrated device may complicate the process and increase the cost of the process.